NE555 Explainer — How a Timer Chip Becomes an Oscillator

Text written by Claude Opus 4.8 (claude-opus-4-8).

NE555 Explainer — How a Timer Chip Becomes an Oscillator

This is the “before you build” companion to Project 6. It assumes you’re comfortable with RC circuits and exponentials, but have never met an IC like this one — no prior electronics needed. The goal: by the end you should be able to derive the pitch formula yourself and know why every wire in the schematic is where it is.

The one piece of jargon you need first: a comparator. It’s a device with two voltage inputs (+ and −) and one output. It does exactly one thing: asks “is the + input higher than the − input?” If yes, the output snaps to its high state (≈ the supply rail); if no, it snaps to low. A one-bit “which input is bigger?” detector with a digital output — no gain, no feedback, no frequency response to track. On a schematic it’s drawn as a triangle with + and − inputs (the same symbol as an op-amp, but don’t read anything op-amp-ish into it — a comparator is the simpler device, built to slam fully to one rail). Everywhere below, “comparator trips” just means “threshold crossed, output flipped.”

The second piece: an SR latch (set–reset flip-flop). It’s a one-bit memory. Two inputs — Set and Reset — and an output Q. Pulse S and the output goes to 1 and stays there even after S returns to rest; pulse R and it goes to 0 and stays. The crucial word is stays: with neither input asserted, the latch holds its last state indefinitely. Physically it’s a bistable element — two stable states held by positive feedback, exactly like a particle sitting in one well of a double-well potential until something kicks it over the barrier. (S and R both asserted at once is the one forbidden/ambiguous input, but the 555’s two comparators can never trip simultaneously, so that case never arises here.) Below, “the latch is set” = output high = capacitor charging; “reset” = output low = discharging.

The punchline up front: the 555 is a hysteretic relaxation oscillator with the hysteresis band pre-wired to ⅓ and ⅔ of the supply. Everything else is packaging. If you’ve ever analysed a Schmitt-trigger-plus-RC relaxation oscillator, you already know the physics — the chip just hands you the comparators and the latch in one 8-pin package.

1. What the thing actually is

The NE555 (1972, Signetics, designed by Hans Camenzind) is an 8-pin analog timer / oscillator chip — one of the best-selling ICs ever made, still manufactured by the billion. It contains roughly two dozen transistors but presents itself as a small number of recognisable functional blocks.

A myth worth puncturing immediately, because you’ll read it everywhere: the “555” is not named after the three 5 kΩ resistors inside it. The chip really does contain a three-resistor divider, and in the original bipolar design those resistors are nominally 5 kΩ each — but Camenzind said in interviews the number was chosen arbitrarily by the marketing manager (Art Fury) because it sounded like it would sell. Nice coincidence, not an etymology.

What it’s meant for: producing precisely-timed events. Two canonical jobs:

• One delay — “wait exactly T seconds after I poke you, then drop the output.” (Monostable / one-shot.)
• A train of pulses — “output a square wave forever at frequency f.” (Astable / oscillator.) This is the mode Project 6 uses.

The reason it’s so beloved is that the timing depends only on an external resistor and capacitor and is independent of the supply voltage (we’ll see why that falls out of the math) — so it’s cheap, stable, and forgiving.

2. The internal architecture (the only diagram that matters)

Five blocks. Map each to something you already know:

            V+ (pin 8)
             │
            ┌┴┐  ── three equal resistors in series form a divider:
            │ │     the two tap points sit at ⅔V+ and ⅓V+
            └┬┘
   ⅔V+ ──────┤────────────►  (−) UPPER comparator   ── compares THRESHOLD (pin 6) to ⅔V+
            ┌┴┐                                          fires when V_C rises ABOVE ⅔V+
            │ │
            └┬┘
   ⅓V+ ──────┤────────────►  (+) LOWER comparator   ── compares TRIGGER (pin 2) to ⅓V+
            ┌┴┐                                          fires when V_C falls BELOW ⅓V+
            │ │
            └┬┘
             │
            GND (pin 1)

   UPPER comparator ── R ─┐
                          │  SR latch ──► OUTPUT stage (pin 3, push-pull)
   LOWER comparator ── S ─┘            └► base of DISCHARGE transistor (pin 7, open collector to GND)

The five blocks:

1. The resistor-divider reference. Three equal resistors from V+ to GND create two fixed reference voltages: ⅔V+ and ⅓V+. These are the comparator trip points. Because they’re fractions of the supply, they track the supply — hold that thought, it’s the reason timing is supply-independent.

2. Upper comparator. Watches the THRESHOLD input (pin 6). When the voltage there climbs above ⅔V+, it trips.

3. Lower comparator. Watches the TRIGGER input (pin 2). When the voltage there falls below ⅓V+, it trips.

4. SR latch (flip-flop). The memory element. Upper comparator → Reset, lower comparator → Set. So once it flips a state it stays there until the other comparator trips. This is exactly the hysteresis you’d build with positive feedback around a single comparator — here it’s done with two comparators and a latch, giving a clean ⅓V+ → ⅔V+ hysteresis band.

5. Output stage + discharge transistor. The latch drives two things in lock-step:

   • Pin 3 (output): a push-pull stage that slams to (near) V+ or (near) GND.
   • Pin 7 (discharge): an open-collector NPN transistor whose collector is pulled to GND whenever the output is low. Think of it as an internal switch to ground that you can hang your timing capacitor’s charging network on.

That’s the whole machine. The genius is that blocks 1–4 form a comparator with built-in hysteresis between ⅓ and ⅔ of the rail, and block 5 gives you both a buffered output and a synchronised switch-to-ground for steering an RC network.

The 8 pins, once

Two pins do nothing useful for us and must still be tied off correctly: pin 4 (reset) → V+ (otherwise stray noise can mute the chip), and pin 5 (control) → a 10 nF cap to GND (keeps divider noise off the threshold; optional but good hygiene). Project 6 later uses pin 5 deliberately for the two-tone siren — nudging the ⅔V+ reference up and down sweeps the pitch.

3. The three modes, briefly

• Monostable (one-shot): the capacitor charges once through one resistor after an external trigger, the output stays high for $T = \ln(3)\,RC \approx 1.1\,RC$, then resets. A timer in the literal sense.
• Bistable (latch): ignore the RC entirely, just use trigger/reset as a set/reset flip-flop. A debounced toggle.
• Astable (free-running oscillator): no external trigger — pins 2 and 6 are tied together so the same capacitor voltage drives both comparators. The chip endlessly chases its own tail between ⅓V+ and ⅔V+, emitting a square wave. This is Project 6. Everything below is this mode.

4. Astable mode: the cycle, in words

Wiring recap (from the project): R1 from V+ to pin 7 (discharge); R2 from pin 7 to the tied pins 6+2; capacitor C from that node to ground. So the node voltage $V_C$ across the capacitor is what both comparators watch.

The cycle is a limit cycle with two phases:

Charging phase (output HIGH). The discharge transistor (pin 7) is off — an open switch. So C charges from the supply through R1 and R2 in series. $V_C$ rises exponentially toward V+. The moment it crosses ⅔V+, the upper comparator trips, resets the latch → output goes LOW and the discharge transistor turns ON.

Discharging phase (output LOW). Pin 7 is now a closed switch to ground. The junction between R1 and R2 is clamped to ~0 V, so C dumps its charge to ground through R2 alone (R1 just bleeds current from the supply into pin 7 — wasted, doesn’t touch C). $V_C$ falls exponentially toward 0. The moment it crosses ⅓V+, the lower comparator trips, sets the latch → output goes HIGH, pin 7 opens, and we’re back to charging.

So $V_C$ is a sawtooth-ish exponential ripple bouncing forever between ⅓ and ⅔ of the rail, and pin 3 is the square wave that rides it. Charge through R1+R2, discharge through R2 — that asymmetry is the whole reason the duty cycle isn’t 50 %, and we’ll quantify it next.

5. Deriving the frequency

This is just the RC relaxation-oscillator calculation; the 555 only fixes the two thresholds for you. Use the universal first-order step response:

so the time to travel from $V_0$ to some $V_1$ toward an asymptote $V_\infty$ is

Charging phase — asymptote $V_\infty = V_{CC}$, time constant $\tau_\text{charge} = (R_1 + R_2)C$, travelling from $V_0 = \tfrac13 V_{CC}$ up to $V_1 = \tfrac23 V_{CC}$:

Discharging phase — asymptote $V_\infty = 0$, time constant $\tau_\text{discharge} = R_2 C$, falling from $\tfrac23 V_{CC}$ to $\tfrac13 V_{CC}$:

Notice the $V_{CC}$ cancels in both logs. The supply sets the absolute voltages but the ratios are fixed at 2:1 by the divider, so the times — and hence the frequency — are completely independent of supply voltage. That is the defining design virtue of the 555, and it falls straight out of “thresholds are fractions of the rail.” (A drifting 4.5 V battery changes loudness, not pitch.)

The period is the sum:

and since $1/\ln 2 = 1.4427$,

The “1.44” you see quoted everywhere (including the project file) is nothing but $1/\ln 2$. Bigger R or bigger C → longer to traverse the same ⅓→⅔ band → lower $f$ → lower pitch. The pitch is the RC time constant made audible.

Duty cycle

Because $R_1 > 0$, this is always > 50 % — the classic 555 astable can’t produce a symmetric square wave from this topology alone. To approach 50 %, make $R_1 \ll R_2$ (then $D \to R_2/2R_2 = \tfrac12$). For audio it barely matters: a square and a near-square wave both sound buzzy. It does shape the timbre — duty cycle sets the harmonic content (a 50 % square has only odd harmonics; moving off 50 % reintroduces even harmonics and changes the “reediness”).

Sanity-check with the project’s values

$R_1 = 1\,\text{k}\Omega$, $R_2 = 10\,\text{k}\Omega$, $C = 10\,\text{nF}$:

a clear, fairly high tone. Duty cycle $D = 11/21 \approx 52\%$ (nicely close to square, because $R_1 \ll R_2$). Swap to $C = 100\,\text{nF}$ and everything scales by 10: $f \approx 690\ \text{Hz}$ — roughly the E above middle C, a much rounder tone. Replacing $R_2$ with the 10 kΩ pot sweeps $f$ continuously over more than a decade as you turn the knob.

6. Practical caveats a physicist will want flagged

These are the things the idealised analysis hides, in rough order of how much they’ll bite you on a breadboard:

• The output doesn’t reach the rail. The bipolar NE555’s push-pull stage drops ~1.5–1.7 V below V+ when sourcing current, and sits ~0.1–0.25 V above ground when sinking. On a 4.5 V supply your “high” is really ≈2.8–3.0 V. Fine for a piezo, but don’t expect a clean 0–4.5 V swing if you scope it. (The CMOS variants below swing much closer to the rails.)
• It’s a current beast for its size. Pin 3 can source/sink ~200 mA. A passive piezo disc is essentially a capacitor (a few nF) and draws almost no real power — you can drive it directly from pin 3. A small magnetic buzzer or a tiny speaker is an inductive/resistive load; driving it directly is fine at these voltages but put a series resistor (~100 Ω) or a small series cap if it gets hot or distorts.
• Supply spikes. Each output transition pulls a brief, sharp current spike through the chip (the push-pull stage momentarily conducts top-to-bottom). On a breadboard with battery leads this shows up as supply ringing and can even cause double-triggering. Put a 100 nF ceramic decoupling cap directly across pins 8 and 1, close to the chip. Cheap insurance; do it by default.
• Don’t make R1 too small. During discharge, R1 carries V+/R1 straight into the discharge transistor. Keep $R_1 \gtrsim 1\,\text{k}\Omega$ so that current stays modest (a few mA) — the project’s 1 kΩ is the conventional floor.
• Pin 4 and pin 5 are not optional. Reset (4) floating → intermittent silence; tie it to V+. Control (5) floating → it works, but a 10 nF cap to GND there cleans up jitter. Skip it only if you’re feeling lucky.
• Tolerances. $f$ inherits the full tolerance of R and C. Ceramic caps are often ±20 % and drift with temperature and voltage, so treat the computed pitch as ±20–30 %. This is a feature for a toy, a nuisance for a clock — for a precise pitch you’d trim with the pot or use a film cap.
• NE555 vs. CMOS 555 (7555/TLC555/LMC555). If you ever want lower power, near-rail-to-rail output, operation below 4.5 V, much higher frequencies, or no supply spikes, the CMOS pin-compatible drop-ins do all of that — at the cost of much lower output current (a few tens of mA) and more static sensitivity. For this project the rugged, high-current bipolar NE555 is the better tool; it’s exactly what makes “just hang the buzzer on pin 3” work.

7. One-paragraph mental model to carry to the breadboard

A capacitor charges through R1+R2, and the chip watches it. At ⅔ of the supply the chip flips its output low and clamps a switch (pin 7) to ground; the capacitor now discharges through R2 until it hits ⅓ of the supply, at which point the chip flips back high and opens the switch. Round and round, between ⅓ and ⅔, forever. Each traversal takes a multiple of $RC\ln 2$, the two thresholds being fixed fractions of the rail is why pitch ignores the battery voltage, and the square wave on pin 3 is what shoves your piezo back and forth into an audible tone. Knob on R2 = knob on the discharge time = knob on the pitch.

← Back to Project 6 · Read Me First

Sources

• 555 timer IC — Wikipedia
• The History of 555 Timer IC — Story of Invention (CircuitsToday)
• The Origin, Explanation, and Applications of Triple-Five Timers — Electronic Design